1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. This application is based on Japanese Patent Applications 2006-347874 and 2007-281918. These disclosures of the above Japanese Patent Applications are incorporated herein by reference.
2. Description of Related Art
Recently, in a semiconductor device, particularly DRAM (Dynamic Random Access Memory), a polymetal gate structure is employed to improve a device operation speed. In the polymetal gate structure, a metal layer is formed on a polysilicon layer, so that this structure can further reduce a word line (sheet) resistance more than a polycide gate structure which was conventionally used. However, when the metal layer (e.g., a tungsten (W) layer) is formed directly on the polysilicon layer, the metal layer reacts with the polysilicon layer in a high temperature thermal treatment to form a metal silicide layer (e.g., a tungsten silicide (WSi) layer) between the polysilicon layer and the metal layer. The metal silicide layer prevents the device from operating at a high speed since it has comparatively high resistance.
In order to cope with this problem, in Japanese Laid Open Patent application (JP-A-Heisei 11-233451), after a silicon layer is formed, a metal nitride layer is deposited on the silicon layer, and a thermal treatment is carried out to react the metal nitride layer with the silicon layer so that a thermally stable barrier layer is formed. A metal layer is formed on the barrier layer. However, when the metal nitride layer is formed directly on the polysilicon layer, the polysilicon layer reacts with the metal nitride layer in a subsequent thermal treatment to form a metal silicide nitride layer. The metal silicide nitride layer has high resistance depending on a composition or a structure of a laminated film. Thus, when the thickness of the laminate film is thick, reduction of the resistance cannot be attained.
Therefore, a technique is demanded which reduces the resistance of a gate electrode in a semiconductor device having a polymetal gate structure.
In conjunction with the above description, the inventor of the present invention proposed the following technique described in Japanese Laid Open Patent Application (JP-P2003-163348A). In the proposal, an impurity doped polysilicon layer, a first refractory metal silicide layer, a first refractory metal nitride layer, and a second refractory metal layer are laminated. Then, the laminated layers are subjected to a thermal treatment. Thus, the first refractory metal silicide layer prevents the first refractory metal layer from reacting with the impurity doped polysilicon layer, so that the silicide layer can be made thinner than a conventional one.
Further, the inventor of the present invention proposed a technique described in Japanese Laid Open Patent Application (JP-P2005-116693A), in which a silicide film of a gate electrode in a P-channel region is formed as a dispersed or discontinuous silicide film. A dual gate structure is formed in the P-channel region and an N channel region adjacent to the P-channel region. In case of the dual gate structure, before gate electrodes are patterned, a polysilicon layer in the N channel region and a polysilicon layer in the P-channel region are in a connected or continuous state. In this case, impurities may mutually diffuse between the polysilicon layers in the N channel region and the P-channel region. It is described in Japanese Laid Open Patent Application (JP-P2005-116693A), that since the mutual diffusion of the impurities is carried out through the silicide layer, the mutual diffusion of the impurities can be prevented by dispersedly or discontinuously forming the silicide layer.
However, a requirement to suppress the diffusion of impurity in the silicon layer becomes harder according to the thinning of the silicon layer for reducing the size of a semiconductor device. When a silicon layer is thinned, it is hard to implant impurity (e.g., boron) into the silicon layer. This is because the impurity penetrates the gate oxide film and is easily implanted into a semiconductor substrate. In order to prevent the impurity from being implanted into the semiconductor substrate, acceleration energy to the impurity is required to be reduced. However, when the acceleration energy of the impurity reduces, an impurity concentration increases in the surface of the silicon layer. When the impurity concentration is high in the surface of the silicon layer, the impurity is easily absorbed by the metal silicide layer, when a thermal treatment is carried out in subsequent process, because the impurity has a larger diffusion coefficient in the metal silicide than that in silicon. Therefore, the impurity is not sufficiently supplied up to a portion of the silicon layer near the gate oxide film. As a result, the operation characteristics of the semiconductor device are degraded due to a depletion layer. Thus, it was made clear that the degradation in the operation characteristics of the semiconductor device accompanied by thinning of the silicon layer could not be completely suppressed even if the above-described conventional techniques were used.